1. Field of the Invention
This invention relates to computer systems and, more particularly, to methods and apparatus for reducing the access time for implementing store operations in a computer system.
2. History of the Prior Art
In computer systems, the access of main memory to retrieve information often takes a substantial portion of the operational time of the system. For this reason, the use of a cache memory to increase system speed has become prevalent in more advanced systems. A cache memory makes use of a relatively small amount of fast random access memory in which recently used instructions and data are stored as they are used by a processor. Such instructions and data are then available in the cache to be accessed by the associated processor more rapidly than they might be in main memory. The basic theory of caching is that, in general, information which has been recently used is more likely to be used sooner than is other information. The cache memory is often both physically faster than the random access memory used for main memory and is arranged so that it may be addressed more rapidly than may main memory. For example, in virtual memory systems, a cache does not need to go through the look-up operation of a memory management unit to determine the physical addresses necessary for accessing main memory. Such caching arrangements have operated to greatly increase the speed of operation of computer systems for certain types of information.
There are many forms of cache memory which may be provided for use with a particular processor. In most of these forms of cache memory, information from a number of different physical locations in main memory may map to the same location in cache memory. Consequently, after some finite period of time, information stored in a position in cache memory may have to be replaced by other information needed by the processor. Some cache memory systems (called write-back systems) do not transfer information written to the cache memory to main memory as soon as it is placed in the cache memory but retain that information until a later more convenient time. Such systems tend to make less use of the system bus and are thus faster.
In a write-back caching arrangement, valid information residing at a position in the cache in which new information is to be stored may not yet have been transferred to main memory so that the storage of the new information would cause the loss of the old information. Thus, data cannot be stored in the cache on a cache miss. For this reason, a store instruction typically requires a check for a cache miss; if there is not a miss, then the accessed information is in the cache, and a store may be accomplished. This check requires an extra clock cycle of operation and causes substantial delay in a pipelined computer system in which it is expected that a command will be executed on each clock cycle.